else, a cache miss occurs and the required word has to be brought The address is compared with the label of all L blocks within that set. Using set field in the memory address, we pierce the particular set of the cache. ![]() Block Bj can be restated into any of the blocks This is appertained to as L- way set- associative mapping. No of BLOCK bits = Number of indicator bits- Number of bits for WORD = 13 – 7 = 6bits No of Index bits = 13 bits( as cache size = 8 KB = 23 × 210 = 213) Number of bits for WORD = 7 bits( as block size = 128 bytes = 27) Number of bits for the physical address = 16 bits( as memory size = 64 KB = 26 × 210 = 216) Size with block size = 128 bytes and say.( Assuming word size = 1 byte) also Still, the size of main memory is = 64 KB, If we've a completely associative counterplotted cache of 8 KB The word is now stored in the cache together with the new label( old label is replaced). else, a cache miss occurs and the required word has to be brought in the cache from the Main For a match, a cache hit do as the required word is set up in theĬache. also, the label bits in the address isĬompared with the label of the block. The BLOCK field of the address is used to pierce the cache’s BLOCK. The address then's divided into 3 fields Label, Block & Word. The process/ fashion of bringing data of main memory blocks into the cache block is known as cacheĮach block from main memory has only one possible place in the cache association in this fashion.įor illustration every block i of the main memory can be counterplotted to block j of the cache using the Still, it's a cache hit differently a cache miss, If data has been set up in the cache. It's a high speed & precious memory.Ĭache hit rate It's the measures how effectively cache fulfills the request for getting content.Ĭache hit rate = No of cache successes( No of cache hits No. It includes small quantum of SRAM & further ![]() Process of prosecution, is known as cache memory. ![]() The small section of SRAM memory, added between main memory and processor( CPU) to speed up the Prerequisite – Cache mapping Types – Direct- mapping, Associative Mapping & Set- Associative Mapping
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